The arithmetic logic circuits include adder-subtracters, dividers, square-root calculators, and the like. The techniques for division and square-root calculation by use of an electronic circuit include the restoring algorithm, the nonrestoring algorithm, the SRT (Sweeney-Robertson-Tocher) algorithm, and the like. In those arithmetic algorithms, an operation for obtaining n digits of a quotient or a square root is repeated, where n is a natural number. The above arithmetic algorithms have a feature that the total number of digits of the quotient or the square root is proportional to the number of repetition of the above operation. Since a subtraction and a digit shift are repeated in the above arithmetic algorithms as in the calculation on paper, the above arithmetic algorithms are hereinafter referred to as subtraction-and-shift type arithmetic algorithms.
The reliability of the subtraction-and-shift type arithmetic circuits can be improved by detecting a malfunction by use of a malfunction detection device. For example, a known malfunction detection circuit generates a malfunction signal when both of a divisor and a dividend are nonzero and both of the most significant digit of an intermediate quotient (which is obtained by a divider in an intermediate stage before normalization of the quotient) and the overflow digit of the quotient (which is located immediately left-adjacent to the most significant digit of the quotient) are zero, so that the malfunction detection circuit can detect a malfunction in which the quotient becomes zero by error.
Incidentally, some of the logic failures found in the subtraction-and-shift type arithmetic logic operations occur only with some patterns of data which are rarely produced during operation. The positions in the subtraction-and-shift type arithmetic circuit in which logical errors as above are likely to occur are known. However, no technique has been found for proving that the logic in such positions is correct. Therefore, currently, the only ways to find a logical failure occurring with a data pattern which is rarely produced are to visually check a drawing or the like of the logic and to collect results of operational verification tests by logic simulations.
Nevertheless, because the capability of appropriate detection of a logic failure by visual checking relies on the ability of the person who visually checks the logical circuit schematic or the like, the reliability of the logic cannot be ensured by the visual checking.
On the other hand, in the case where the objective circuit is as small as a single operating element, the results of operational verification tests can be collected for a sufficiently long time, and therefore the detection of a logic failure by logic simulations can ensure high reliability. However, in the case where the objective circuit is as large as the subtraction-and-shift type arithmetic circuit, it is difficult to ensure sufficient reliability even when the operational verification tests by logic simulations are performed. That is, the time which can be spent for checking each operational element is limited when verification of a large-scale system is performed by logic simulations or is performed on the real system. Because of such a limitation by time, it is difficult to find a bug in the subtraction-and-shift type arithmetic circuit by logic simulations. Thus, conventionally, improvement in the quality of the logic of the arithmetic circuit is limited.
Even in the case where a failure cannot be completely avoided in advance by the operational verification tests, the reliability can be secured if it is possible to prevent an erroneous calculation result from being passed to a subsequent processing stage. Therefore, there is a demand for a technique for detecting a malfunction with high reliability even in the case where the malfunction rarely occurs during operations for calculation.
[Patent Document 1] Japanese Laid-open Patent Publication No. 62-212728.